Synchronizing circuit employing plural bistable-elements for producing low frequency output in synchronism with low and high frequency inputs



April 2, 1968 c w 3,376,435

SYNGHRONIZING CIRCUIT EMPLOYING PLURAL BISTABLE-ELEMENTS FOR PRODUCINGLOW FREQUENCY OUTPUT IN SYNCHRONISM WITH LOW AND HIGH FREQUENCY INPUTSOriginal Filed June 1. 1962 2 Sheets-Sheet 1 JNVENTO 8%92/5 M nvF April2, 1968 c. M. WINE 3,375,435

SYNCHRONIZING CIRCUIT EMPLOYING PLURAL BISTABLE-ELEMENTS FOR PRODUCINGLOW FREQUENCY OUTPUT IN SYNCHRONISM WITH LOW AND HIGH FREQUENCY INPUTSOriginal Filed June 1, 1962 2 Sheets-Sheet 2 A A A A A ML m pz/r mama 0I j I v Jim 0 (5) I A A A A A 521/6 0 k I l a l (a) X fl/vijr s I I Fj.2.

Ina/ail United States Patent 11 Claims. c1. s07 2s9 This application isa continuation of application Ser. No. 199,288, filed June 1, 1962, andnow abandoned by Charles M. Wine for Synchronizing Circuit.

This invention relates generally to synchronizing circuits, andparticularly to an improved circuit for producing output trigger pulsesat a relatively low repetition rate and in fixed phase relationship withinput signals at a relatively much higher repetition rate. The improvedsynchronizing circuit of the present invention is particularly usefulfor applying synchronized pulses to the deflection circuits of asampling oscilloscope so that the sampled pulse is in time coincidencewith a fixed point or phase on the input signal to be observed.

In order to observe high speed, repetitive signals with a samplingoscilloscope, a low frequency trigger pulse, properly synchronized withthe signal to be observed, is employed. The most common means forobtaining such trigger pulses in the prior art are synchronizingcircuits that count down (frequency divide) from the high frequencyinput signals. These prior art circuits produce trigger pulses havingtwo distinct characteristics. Firstly, the start of each trigger pulseis fixed in time with respect to a reference point of each n cycle ofthe high frequency input signal. Secondly, the repetition rate of thetrigger pulses is an integral sub-multiple of the repetition rate of thehigh frequency input signal. Such count-down synchronizing circuits arerelatively complex and expensive. In circuits of the present invention,the frequency of the low frequency trigger pulses is not necessarily anintegral sub-multiple of the frequency of the high frequency inputsignals. In accordance with the present invention, the leading edge ofeach output, low frequency trigger pulse is, however, fixed in phase, orcoincidence, with a fixed point (a definite fixed phase) on selectedcycles of the high frequency input signal.

It is an object of the present invention to provide an imrpovedsynchronizing circuit that is less complex than synchronizing circuitsof the prior art, relatively free from time jitter, and yet highlyefiicient in use.

In accordance with the present invention, the improved synchronizingcircuit comprises a relatively low frequency oscillator and two bistablecircuits. Each of the bistable circuits has both high and low voltagestable states. The oscillator circuit and the high frequency inputsignals are applied to the first bistable circuit to cause it to switchfrom its low voltage state to its high voltage state periodically at thefrequency of the oscillator circuit. The output of the first bistablecircuit is applied to the second bistable circuit. The high frequencyinput signals are also applied to the second bistable circuit through adelay circuit. The second bistable circuit is biased so that it willswitch from its low voltage state to its high voltage state only uponthe application thereto of both the high voltage output from the firstbistable circuit and a delayed one of the high frequency input signals.Means are also provided to reset the bistable circuits periodically atthe frequency of the oscillator circuit. The output, low frequencytrigger pulses, synchronized with high frequency input signals, in thesense of having a fixed phase relationship with the input pulses, arederived from the second bistable circuit.

The novel features of the present invention, both as to its organizationand method of operation, as well as additional objects and advantagesthereof, will be more readily understood from the following description,when read in connection with the accompanying drawings, in which thesame reference characters designate similar parts throughout, and inwhich:

FIG. 1 is a schematic diagram, partly in block form, of an improvedsynchronizing circuit in accordance with the present invention,

FIG. 2 is a series of waveforms used to explain the operation of thesynchronizing circuit in FIG. 1; and

FIGS. 3 and 4 are current-voltage (I-V) characteristics of components ofthe synchronizing circuit shown in FIG. 1.

Referring, now, particularly to FIG. 1, there is shown a synchronizingcircuit 10 for providing between its output terminals 12 and 14relatively low frequency trigger pulses in synchronism with relativelymuch higher frequency signals applied to input terminals 16 and 18. Theterminals 14 and 18 are connected to a common terminal, such as ground.The synchronizing circuit 10 comprises an oscillator circuit 20, such asa transistor astable multivibrator, adapted to provide oscillations of arelatively low frequency, e.g., the frequency of the trigger pulses tobe provided between the output terminals 12 and 14. The oscillations ofthe oscillator 20 may be square waves having the waveform 0 shown inFIG. 2. Typical high frequency input signals and output trigger pulsesare shown respectively by the waveforms a and f, in FIG. 2.

The synchronizing circuit 10 comprises two bistable circuits having twotunnel diodes D1 and D2, respectively. The diodes D1 and D2 are negativeresistance diodes of the type having high and low voltage stable states,depending upon the amplitude of the current applied to them.

The diode D1 is connected to operate as a threshold gate circuit. Tothis end, the output of the oscillator 20 is connected across the diodeD1 through a resistor 22. The amplitude of each positive-going pulse 0(FIG. 2) of the oscillator 20 is sufiicient to switch the diode D1 fromits low voltage state to its high voltage state. The high frequencyinput signals a (FIG. 2), applied between the input terminals 16 and 18of the circuit 10, are also applied across the diode D1 through aresistor 24. It will now be understood that although the periodic pulsesfrom the oscillator 20 alone are adapted to switch the diode D1 from itslow voltage state to its high voltage stable state at the frequency ofthe oscillator 20, the high frequency input signals a aid in theswitching action of the diode D1 by adding to the amplitude of thepulses from the oscillator 20.

The diode D2 is connected to function as an AND gate. To this end, theoutput from the diode D1 is connected across the diode D2 through aresistor 26. The high frequency input signals a, applied between theinput terminals 16 and 18, are also applied across the diode D2 througha delay circuit, such as the delay line 28 connected in series with aresistor 30. The delay line 28 is shielded and grounded. The diode D2 isbiased in its low voltage state by means of a source of unidirectionalvoltage (not shown) applied across the diode D2 through a resistor 32.The positive terminal of the unidirectional voltage source is connectedto a terminal 33. The output of the diode D2 is applied to the outputterminals 12 and 14 through a resistor 35. The output from the diode D1,even in its high voltage state, is insufficient to switch the diode D2to its high voltage state in the absence of the application of adelayed, input high frequency signal also across diode D2. It will beunderstood, therefore, that an output trigger pulse 1 from the diode D2can be obtained only by the application thereto of both a voltage 2 fromthe diode D1 when the latter is in its high voltage state and a delayed,high frequency input signal b.

Means are provided to return the diodes D1 and D2 to their low voltagestates periodically after they have been switched to their high voltagestates. The diode D1 is returned to its low voltage state periodicallywhen each pulse from the oscillator 20 reaches zero. Since the anode ofthe diode D2 is biased positively with a steady bias, the pulses c fromthe oscillator 20 are differentiated and clipped, and the resulting,negative-going pulses are applied periodically to the anode of the diodeD2 to switch it to its low voltage state; To this end, the output of theoscillator 20 is connected across a capacitor 34 in series with aresistor 36 to differentiate the output pulses of the oscillator 20. Thedifferentiated pulses are clipped by a diode 38 connected from thecommon junction of the I capacitor 34 and the resistor 36 to the anodeof the diode D2. The diode 38 is poled so as to apply only negativegoingpulses d (FIG. 2) periodically to the diode D2.

Referring, now, to FIGS. 3 and 4, there are shown the I-Vcharacteristics of the diodes D1 and D2, respectively. In FIG. 3, thelow and high voltage steady states of the diode D1 are indicatedrespectively by the points L and H, the points of intersection betweenthe I-V characteristic curve and the two load lines representing the lowand high output voltage limits of the oscillator circuit 20.

In FIG. 4, the point L' represents a low voltage steady state of thediode D2. The point LL is substantially equal to the point L in voltageand also represents the low voltage steady state of the diode D2. Thevoltage L is the voltage across the diode D2 supplied by the biasingvoltage from the steady, bias voltage source, and the voltage LLrepresents the voltage across the diode D2 upon the application theretoof only the output from the diode D1 when the latter is high. Thevoltage point H represents the voltage across the diode D2 in its highvoltage steady state, occurring upon the application thereto of both adelayed input signal and the high voltage output from the diode D1.

The waveforms a f in FIG. 2 represent the voltages occurring at thepoints a f in the circuit 10 in FIG. 1, but the amplitudes of thesewaveforms are not to scale.

The operation of the synchronizing circuit 10 will now be explained. Letit be assumed that the frequency of the repetitive input signals a,applied between the input terminals 16 and 18, is 500 megacycles persecond. Let it also be assumed that about every millionth signal issampled, whereby to produce output trigger pulses at a relatively lowerrepetition rate, say, about 500 cycles per second, for example, betweenthe output terminals 12 and 14. Thus, the frequency of the outputtrigger pulses f is reduced with respect to the frequency of the inputsignals a by about 10 The oscillator 20 is adjusted, by any means wellknown in the art, to produce pulses c of the desired low frequencytrigger pulses, namely, about 500 c.p.s. Pulses c from the oscillator 20cause the diode D1 to be switched periodically between its low and itshigh voltage states at this low frequency. The pulses e produced at theoutput of the diode D1 have a small amount of time jitter J, as shown bythe shaded area of the waveform e in FIG. 2. The amount of time jitteris a function of the amplitude of overdrive applied to the diode D1.Since the diode D1 is switched from its low voltage, steady state to itshigh voltage, steady state either by a pulse c from the oscillator 20 orby the combination of the pulse 0 and the input signal a, the ampli tudeof the overdrive may vary each time the diode D1 is switched; hence, thejitter J. The amount of delay produced by the delay line 28 is at leastas long as the maximum jitter I, but it is less than one cycle of thehigh frequency input signal a. The high voltage output from the diode D1and the delayed input pulse b are applied across the diode D2 to switchthe latter from its low voltage state L, LL to its high voltage state Hto provide the output trigger pulses f. The output trigger pulses f maybe amplified, if necessary. The jitter is absent in the leading edge ofthese output pulses. These leading edges occur in fixed phase relationto the high frequency input pulses. Hence there is substantially nojitter, on the oscilloscope if the oscilloscope is synchronized with theleading edge of the output pulses of the diode D2.

The diode D1 is returned to its low voltage state L periodically everytime the oscillator pulses c drop to zero, and the diode D2 is returnedto its low voltage state L' periodically by the differentiated andclipped pulses d, shown in FIG. 2.

It is noted that the diode D2 is switched periodically to its highvoltage state with substantially no jitter because it is always switchedwith the combined, relatively large, constant amplitudes of high voltageoutput pulses e from the diode D1 and the delayed input signal b. Thus,the leading edges of the output trigger pulses f of diode D2 are alwaysinitiated in fixed phase relationship with the delayed input signalb,-and the delayed, high frequency input signals b may be sampled by asampling oscilloscope when the horizontal sweep circuit of the samplingoscilloscope is triggered by the relatively low frequency triggerpulses 1. For example, the output pulses from D2 may be initiated at then input signal, the Zn-l-l input signal, and perhaps the 3n--1 inputsignal. Nevertheless, the desired, jitter-free, initiation of the outputpulses in fixed phase relationship to the input signals is preserved.

From the foregoing description, it will be apparent that there has beenprovided an improved synchronizing circuit adapted to provide relativelylow frequency trigger pulses for observing repetitive, relatively highfrequency 1 signals with the aid of a sampling oscilloscope. The circuitmay be incorporated in theoscilloscope. While only one embodiment andapplication of the invention has been described, various componentsuseful therein, as well as variations in the circuitry coming within thespirit of this invention, will, no doubt, readily suggest themselves tothose skilled in the art. Hence, it is desired that the foregoing shallbe considered merely as illustrative and not in a limiting sense.

What is claimed is:

1. A synchronizing circuit for producing output pulses at a relativelylow repetition rate in synchronism with input signals at a relativelyhigher repetition rate, said synchronizing circuit comprising,

an oscillator circuit providing pulses of the frequency of said lowrepetition rate,

two tunnel diodes each'having high and low voltage stable states,

means connecting said oscillator circuit to one of said diodes to switchit periodically from its low voltage state to its high voltage state,

means connecting said one diode to the other of said diodes to apply theoutput of said one diode to said other diode,

a delay circuit,

means to apply said input signals to said one diode,

means to apply said input signals to said other diode through said delaycircuit to switch said other diode from its low voltage state to itshigh voltage state only upon application thereto of both a delayedone ofsaid input signals and said output from said one diode when said onediode is in its high voltage state,

said delay circuit delaying said input signal an amount less than onecycle of said input signal at said higher repetition rate, and means toderive said output pulses from said other diode. 2. A synchronizingcircuit for producing output pulses at a relatively low repetition ratein synchronism with input pulses at a relatively higher repetition rate,said synchronizing circuit comprising,

an oscillator circuit providing pulses of the frequency of said lowrepetition rate,

a threshold circuit and an AND circuit each comprising a tunnel diodehaving high and low voltage stable states,

means connecting said oscillator circuit to said threshold circuit toswitch said threshold circuit periodically from its low voltage state toits high voltage state,

means connecting said threshold circuit to said AND circuit to apply theoutput of said threshold circuit to said AND circuit,

a delay circuit,

means to apply said input signals to said threshold circuit,

means to apply said input signals to said AND circuit through said delaycircuit,

means to bias said AND circuit so that it is switched from its lowvoltage state to its high voltage state only upon the applicationthereto of both a delayed one of said input signals and said output fromsaid threshold circuit,

means connecting said oscillator circuit to said AND circuit to switchit periodically from said high voltage state to said low voltage state,and

means to derive said output pulses from said AND circuit.

3. A circuit for synchronizing output pulses of a relatively lowfrequency with repetitive input signals of a relatively higherfrequency, said circuit comprising,

an oscillator circuit providing pulses of said low frequency,

first and second tunnel diodes each having high and low voltage stablestates,

means to apply said input signals and pulses from said oscillator tosaid first diode, each of said pulses from said oscillator being of asufiicient amplitude to switch said first tunnel diode from its lowvoltage state to its high voltage state,

means to connect the output of said first tunnel diode to said secondtunnel diode,

a delay line,

means to connect said input signals to said second tunnel diode throughsaid delay line,

means to bias said second tunnel diode so that it is switched from itslow voltage state to its high voltage state only upon the applicationthereto of both a delayed one of said input signals and said output ofsaid first tunnel diode when said first tunnel diode is in a highvoltage state,

said delay circuit delaying said input signals an amount less than onecycle of said input signal at said higher frequency, and

means to derive said output pulses from said second diode.

4. A circuit for synchronizing relatively low frequency output pulseswith relatively higher frequency input signals, said circuit comprising,

an oscillator providing pulses of the frequency of said low frequencyoutput pulses,

first and second tunnel diodes each having high and low voltage stablestates,

means to apply said oscillator pulses and said input signals across saidfirst diode to switch said first diode periodically between its low andhigh voltage states,

means to connect the output of said first diode across said seconddiode,

a delay line,

means to connect said input signals across said second diode throughsaid delay line,

means to bias said second diode so as to cause it to switch from saidlow voltage state to said high voltage state only upon the applicationthereto of both said output of said first diode and a delayed one ofsaid input signals,

means connected between said oscillator and said sec- 0nd diode toswitch said second diode periodically from its high voltage state to itslow voltage state, and

means to derive said output pulses across said second diode.

5. A circuit for synchronizing relatively low frequency output pulseswith relatively higher frequency input signals, said circuit comprising,

an oscillator providing pulses of the frequency of said low frequencyoutput pulses,

first and second tunnel diodes each having high and low voltage stablestates,

means to apply said oscillator pulses and said input signals across saidfirst diode to switch said first diode periodically between its low andhigh voltage states,

means to connect the output of said first diode across said seconddiode,

a delay line,

means to connect said input signals across said second diode throughsaid delay line,

means to bias said second diode so as to cause it to switch from saidlow voltage state to said high voltage state only upon the applicationthereto of both said output of said first diode and a delayed one ofsaid input signals,

means to differentiate said oscillator pulses to obtain differentiatedpulses,

means to clip said differentiated pulses to obtain clipped ulses,

means to apply said clipped pulses periodically across said second diodeto cause it to switch periodically from its high voltage state to itslow voltage state, and

means to obtain said output pulses across said second diode.

6. In combination,

a threshold circuit and a bistable device each having a set and resetcondition, both quiescently in said reset condition,

means for applying first pulses at a relatively low repetition rate andof relatively long duration, and second pulses at a relatively highrepetition rate and of relatively short duration, and of the samepolarity as said first pulses, to said threshold circuit forperiodically switching said threshold circuit to its set condition,

means for delaying said second pulses an interval not integrally relatedto that between said second pulses, and

means for applying said delayed second pulses and the output of saidthreshold circuit, both in the same polarity, to said bistable devicefor switching said bistable device to its set condition in response tothe receipt by said bistable device of said delayed second pulses duringthe intervals said threshold circuit is in its set condition.

7. In combination,

a threshold circuit and a bistable device a set and reset condition,both reset condition,

means for applying first pulses at a relatively low repetition rate andof relatively long duration, and second pulses at a relatively highrepetition rate and of relatively short duration, and of the samepolarity as said first pulses, to said threshold circuit with said firstand second pulses being at an amplitude level such that either pulsesperiodically switch aid threshold circuit to its set condition,

means for delaying said second pulses an interval somewhat less thanthat between said second pulses, and

means for applying said delayed second pulses and the output of saidthreshold circuit, both in the same polarity, to said bistable devicefor switching said bistable device to its set condition in response tothe receipt by said bistable device of said delayed second each havingquiescently in said pulses during the intervals said threshold circuitis in its set condition.

8. In combination,

a threshold circuit and a bistable device each having a set and resetcondition, both quiescently in said reset condition,

means for applying first pulses at a relatively low repetition rate andof relatively long duration, and second pulses at a relatively highrepetition rate and of relatively short duration, and of the samepolarity as said first pulses, to said threshold circuit, both at anamplitude level such that either pulses switch said threshold circuit toits set condition for an interval determined by the duration of saidpulses,

means for delaying said second pulses an interval somewhat less thanthat between said second pulses,

means for applying said delayed second pulses and the output of saidthreshold circuit, both in the same polarity, to said bistable devicefor switching said bistable device to its set condition in response tothe receipt by said bistable device of said delayed second pulses duringthe intervals said threshold circuit is in its set condition, and

means responsive to the lagging edge of said first pulses for resettingsaid bistable device to its original reset condition.

9. In combination,

two tunnel diodes capable of assuming either one of a first and secondvoltage state, both quiescently biased to said first voltage state,

means for applying first pulses at a relatively low repetition rate anda relatively long duration, and second pulses at a relatively highrepetition rate and a relatively short duration, and of the samepolarity as the first pulses to said first tunnel diode for periodicallyswitching the same to its said second voltage state,

means for delaying said second pulses an interval somewhat less than theinterval between said second pulses, and

means for applying said delayed second pulses and the output of thefirst tunnel diode in the same polarity to said second tunnel diode forswitching said second tunnel diode to its said second voltage state inresponse to the receipt by said second tunnel diode of a delayed one ofsaid second pulses during the interval said first tunnel diode is in itssaid second voltage state.

10. In combination,

two tunnel diodes, the first quiescently monostably biased to a givenvoltage state and the second quiescently bistably biased to the samevoltage state,

means for applying first pulses at a relatively low repetition rate anda relatively long duration, and second pulses at a relatively highrepetition rate and a relatively short duration, and of the samepolarity as the first pulses to said first tunnel diode, either pulsesbeing of sufficient amplitude to switch said second tunnel diode to itsother voltage state,

means for delaying said second pulses an interval somewhat less than theinterval between said second pulses, and

means for applying said delayed second pulses and the output of thefirst tunnel diode in the same polarity to said second tunnel diode forswitching said second tunnel diode to its other voltage state inresponse to the receipt by said second tunnel diode of a delayed secondpulse during the interval said first tunnel diode is in its said othervoltage state.

11. In combination,

two tunnel diodes, the first quiescently monostably biased to a givenvoltage state and the second quiescently bistably biased to the samevoltage state, means for applying first pulses at a relatively lowrepetition rate and a relatively long duration, and sec- 0nd pulses at arelatively high repetition rate and of relatively short duration, and ofthe same polarity as the first pulses, to said first tunnel diode forperiodically switching the same to its other voltage state, means fordelaying said second pulses an interval somewhat less than the intervalbetween said second pulses, means for applying said delayed secondpulses and the output of said first tunnel diode in the same polarity tosaid second tunnel diode for switching said second tunnel diode to itsother voltage state in response to the receipt by said second tunneldiode of a delayed one of said second pulses during the interval saidfirst tunnel diode is in its said other voltage state, and meansresponsive to the lagging edge of said first pulses for switching saidsecond tunnel diode from its said other voltage state to its originalvoltage state.

References Cited UNITED STATES PATENTS 2,512,152 6/1950 Haworth et a1.328-55 3,099,712 7/1963 Meacham 328-72 X 3,188,484 6/1965 Jorgensen307-885 3,196,358 7/1965 Bagley 30788.5

JOHN S. HEYMAN, Primary Examiner,

1. A SYNCHRONIZING CIRCUIT FOR PRODUCING OUTPUT PULSES AT A RELATIVELYLOW REPETITION RATE IN SYNCHRONISM WITH INPUT SIGNALS AT A RELATIVELYHIGHER REPETITION RATE, SAID SYNCHRONIZING CIRCUIT COMPRISING, ANOSCILLATOR CIRCUIT PROVIDING PULSES OF THE FREQUENCY OF SAID LOWREPETITION RATE, TWO TUNNEL DIODES EACH HAVING HIGH AND LOW VOLTAGESTABLE STATES, MEANS CONNECTING SAID OSCILLATOR CIRCUIT TO ONE OF SAIDDIODES TO SWITCH IT PERIODICALLY FROM ITS LOW VOLTAGE STATE TO ITS HIGHVOLTAGE STATE, MEANS CONNECTING SAID ONE DIODE TO THE OTHER OF SAIDDIODES TO APPLY THE OUTPUT OF SAID ONE DIODE TO SAID OTHER DIODE, ADELAY CIRCUIT, MEANS TO APPLY SAID INPUT SIGNALS TO SAID ONE DIODE,MEANS TO APPLY SAID INPUT SIGNALS TO SAID OTHER DIODE THROUGH SAID DELAYCIRCUIT TO SWITCH SAID OTHER DIODE FROM ITS LOW VOLTAGE STATE TO ITSHIGH VOLTAGE STATE ONLY UPON APPLICATION THERETO OF BOTH A DELAYED ONEOF SAID INPUT SIGNALS AND SAID OUTPUT FROM SAID ONE DIODE WHEN SAID ONEDIODE IS IN ITS HIGH VOLTAGE STATE, SAID DELAY CIRCUIT DELAYING SAIDINPUT SIGNAL AN AMOUNT LESS THAN ONE CYCLE OF SAID INPUT SIGNAL AT SAIDHIGHER REPETITION RATE, AND MEANS TO DERIVE SAID OUTPUT PULSES FROM SAIDOTHER DIODE.